ECE - 342 EXPERIMENT IX Week 13 Spring 2010 (4/13/2010)
In this experiment, you will examine the ways to interface the TTL family and the CMOS logic family of digital integrated circuits. Also, you will design and build an astable multivibrator using CMOS NAND gates.
1 - 4011 Quad 2-input CMOS NAND gate
1 - 7400 Quad 2-input TTL NAND gate
2 - 2N3053 NPN transistor
CMOS Transmission gate
1. TTL-to-CMOS Interface
When used with a 5-V power supply, CMOS is somewhat compatible with TTL. In the Low state, a TTL output can drive CMOS directly. However, the guaranteed TTL HIGH output level of 2.4 V is not a valid input level for CMOS. If a TTL output drives only CMOS, then there is essentially no output current and the HIGH output level may be 3.5 V or higher. Whether this is sufficient for a reliable interface depends on the exact manufacturer's specifications for both the TTL outputs and the CMOS inputs. A valid HIGH output level can always be ensured by typing a pull-up resistor from the TTL output to the 5 V supply.
2. CMOS-to-TTL Interface
When CMOS drives TTL the HIGH state is not a problem. The crucial question is whether CMOS can sink TTL input current in the LOW state without exceeding the maximum value of the TTL LOW-state input voltage. The reason for this is that when the input of a TTL gate is LOW, the input transistor is conducting in the forward direction. Therefore a current is flowing out of one of the emitters of the input transistor, and this current must flow into the circuit connected to the TTL input. Typical CMOS gates are specified to sink about 0.4 mA in the LOW state while maintaining an output voltage of 0.4 volts or less. This is sufficient to drive two low-power TTL inputs or one low-power Schottky input, but it is insufficient to drive standard TTL. Close examination of the specifications may show that it is possible to drive standard TTL at room temperature with some loss of DC noise margin. However, it is better to use a special buffer such as a 4041 to drive standard TTL from CMOS.
3. CMOS Transmission Gate
The CMOS transmission gate circuit and circuit symbols are indicated in figure 3. The transmission gate transfers the input signal to the output, if and only if C is HIGH and is LOW. These transmission gates are made using MOSFETs with positive threshold voltages. When the input is HIGH then the source-to-gate voltage of the PMOS transistor is a large enough to turn on the PMOSFET. This creates a conducting channel between the input and output terminals. If the input signal is LOW then the gate-to-source voltage of the NMOS transistor is large enough to turn the NMOSFET on, again creating a conducting channel between input and output. If C is LOW and HIGH then both MOSFETs are off no matter what the input signal is.
1. TTL/CMOS interface
a Simple interfacing Build the circuits shown in figure 1. Measure the propagation delay from input to output of a TTL pulse.
b. TTL/CMOS interface using an npn transistor. Wire the circuit as shown in figure 2. Adjust the frequency of the clock so that the LED monitor flashes approximately once each second. The npn transistor is used to overcome the incompatible logic levels that exist between the TTL driver and the CMOS load. When used, the transistor stage inverts the input signal so that when the input to the transistor stage is at (TTL) logic 1, the collector voltage is essential at 0 volts since the transistor is driven into saturation. When the input is zero (TTL-logic 0), the collector voltage is nearly that of the CMOS supply, since the transistor is cut off. Increase the supply voltage VDD from 3 volts to 15 volts. Is there any difference in the operation of the circuit?
2. CMOS Transmission Gate
Set up the circuit of figure 4. Sketch the input and output waveforms. Measure the propagation delay of the CMOS transmission gate. Now set C LOW (0 V) and C HIGH (5.0 V). What output signal do you see?
(Hint: Use the QUAD analog switch in your kit)